在深入了解Flash存储器的基础上，采用单片机自动检测存储器无效块。主要通过读取每一块的第1、第2页内容，判断该块的好坏，并给出具体的实现过程，以及部分关键的电路原理图和C语言程序代码。该设计最终实现单片机自动检测Flash坏块的功能，并通过读取ID号检测Flash的性能，同时该设计能够存储和读取1GB数据。 Abstract: On the basis of in-depth understanding the Flash chips，this paper designs a new program which using the SCM to detect the invalid Block.Mainly through reading the data of the first and second page to detect the invalid Block.Specific implementation procedure was given,and the key circuit schematic diagram and C language program code was introduced.This design achieved the function of using the MCU checks the invalid Block finally，and increased the function by reading the ID number of Flash to get the performance of the memory.And the design also can write and read1GB data
上传时间： 2013-10-25
上传用户：taozhihua1314
介绍了电力操作电源与智能电池巡检系统的特点，给出了一种基于超低功耗单片机MSP430 F149针对中小型变电站自动化运行的专用设备的基本设计原理及实现方法，最后给出了详细硬件构成和软件实现。该系统能满足中小型变电站安全、可靠、自动运行的要求，并通过与上位机的串行通信实现变电站的远程管理和控制。 Abstract: The characters of the intelligent battery data logging system of the electric operation power are introduced.The basic design principle and the implemented methods of the special equipment which only designed for the middle or small transformer substation based on MSP430F149 are prescribed. Finally, the hardware Block diagram and the software flow chart are also given. The function that the system finally needs to realize can basically meet with the middle or small transformer substation’s satisfy, reliably,and automatic running.And it can also realize the transformer substation long-distance management and control by serial communicating with the host computer.
上传时间： 2013-11-25
上传用户：黄华强
The LPC1769/68/67/66/65/64 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support Block integration.
上传时间： 2014-02-20
上传用户：13215175592
The LPC1700 Ethernet Block contains a full featured 10 Mbps or 100 Mbps Ethernet MAC (Media Access Controller) designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with Scatter-Gather DMA off-loads many operations from the CPU.
上传时间： 2013-11-09
上传用户：geshaowei
本文介绍了一种基于单片机的健身车转速测量系统。该系统具有电路简单、使用方便等特点。文中详细介绍了该系统的工作原理,并且给出了它的硬件原理图和软件设计程序框图。关键词:转速 单片机 测量ABSTRACT :This paper introduces a measuring system of the rotational velocity of exercise bike based on single - chip microcomputer . It has such advantages : simple circuit ,convenient use and so on. The work principle is presented in detail in this paper and the Block diagram of hardware and program flow chart are giv2 en as well .KEYWORDS :Rotational velocity Single - chip microcomputer Measuring
上传时间： 2013-11-02
上传用户：源弋弋
The ISO7220 and ISO7221 are dual-channel digital isolators. To facilitate PCB layout, the channels are orientedin the same direction in the ISO7220 and in opposite directions in the ISO7221. These devices have a logic inputand output buffer separated by TI’s silicon-dioxide (SiO2) isolation barrier, providing galvanic isolation of up to4000 V. Used in conjunction with isolated power supplies, these devices Block high voltage, isolate grounds, andprevent noise currents on a data bus or other circuits from entering the local ground and interfering with ordamaging sensitive circuitry.
上传时间： 2013-10-24
上传用户：hbsunhui
In this document, the term Ô60xÕ is used to denote a 32-bit microprocessor from the PowerPC architecture family that conforms to the bus interface of the PowerPC 601ª, PowerPC 603ª, or PowerPC 604 microprocessors. Note that this does not include the PowerPC 602ª microprocessor which has a multiplexed address/data bus. 60x processors implement the PowerPC architecture as it is speciÞed for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits,and ßoating-point data types of 32 and 64 bits (single-precision and double-precision).1.1 Overview The MPC106 provides an integrated high-bandwidth, high-performance, TTL-compatible interface between a 60x processor, a secondary (L2) cache or additional (up to four total) 60x processors, the PCI bus,and main memory. This section provides a Block diagram showing the major functional units of the 106 and describes brießy how those units interact.Figure 1 shows the major functional units within the 106. Note that this is a conceptual Block diagram intended to show the basic features rather than an attempt to show how these features are physically implemented on the device.
上传时间： 2013-10-08
上传用户：18711024007
支持40 GbE、100 GbE和Interlaken的高密度硬核MLD/PCS模块，从而提高系统集成度。 宽带数据缓冲，提供1,600-Mbps外部存储器接口。 数据包处理和流量管理功能的高效实现。 更高的系统性能，同时保持功耗和成本预算不变。
上传时间： 2013-11-23
上传用户：asdgfsdfht
基于RAM块的应用
上传时间： 2013-11-02
上传用户：box2000
This application note describes how the existing dual-port Block memories in the Spartan™-IIand Virtex™ families can be used as Quad-Port memories. This essentially involves a dataaccess time (halved) versus functionality (doubled) trade-off. The overall bandwidth of the Blockmemory in terms of bits per second will remain the same.
上传时间： 2013-11-08
上传用户：lou45566
