Verilog, c and asm source codes of the Minimig system, a fpga implementation of the Amiga computer. Version minimig-j used on the Minimig fpga board.
标签： implementation the computer Verilog
上传时间： 2017-09-24
上传用户：xauthu
This book describes how global mobile communication was made. It is written for those who want or need to know how this was achieved e.g.: † Young professionals who want to build their career on GSM and UMTS and need to understand the basics † Strategic and technical planners who want to drive the future GSM and UMTS develop- ment † Strategists who plan to repeat GSM’s success in the fourth generation † Academics, who want to understand and analyse the development of GSM and UMTS; † Activists in other large scale international communication projects who want to use experiences gained
标签： Creation UMTS GSM and The of
上传时间： 2020-05-27
上传用户：shancjb
Data Structures and Algorithms with Object-Oriented Design Patterns in Java Bruno R. Preiss B.A.Sc., M.A.Sc., Ph.D., P.Eng. Associate Professor Department of Electrical and Computer Engineering University of Waterloo, Waterloo, Canada
标签： B.A.S R. Object-Oriented Algorithms
上传时间： 2017-03-06
上传用户：z754970244
We have a group of N items (represented by integers from 1 to N), and we know that there is some total order defined for these items. You may assume that no two elements will be equal (for all a, b: a<b or b<a). However, it is expensive to compare two items. Your task is to make a number of comparisons, and then output the sorted order. The cost of determining if a < b is given by the bth integer of element a of costs (space delimited), which is the same as the ath integer of element b. Naturally, you will be judged on the total cost of the comparisons you make before outputting the sorted order. If your order is incorrect, you will receive a 0. Otherwise, your score will be opt/cost, where opt is the best cost anyone has achieved and cost is the total cost of the comparisons you make (so your score for a test case will be between 0 and 1). Your score for the problem will simply be the sum of your scores for the individual test cases.
标签： represented integers group items
上传时间： 2016-01-16
上传用户：jeffery
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
上传时间： 2013-10-23
上传用户：copu
Description: S-ISOMAP is a manifold learning algorithm, which is a supervised variant of ISOMAP. Reference: X. Geng, D.-C. Zhan, and Z.-H. Zhou. Supervised nonlinear dimensionality reduction for visualization and classification. IEEE Transactions on Systems, Man, and Cybernetics - Part B: Cybernetics, 2005, vol.35, no.6, pp.1098-1107.
标签： Description supervised algorithm S-ISOMAP
上传时间： 2015-04-10
上传用户：wfeel
Quality, object.oriented architecture is the product of careful study, decision making, and experimentation. At a minimum, the object.oriented architecture process includes farming of requirements, architecture mining, and hands.on experience. Ideally, object.oriented architecture comprises a set of high.quality design decisions that provide benefits throughout the life cycle of the system.
标签： architecture decision oriented Quality
上传时间： 2014-10-28
上传用户：love_stanford
The government of a small but important country has decided that the alphabet needs to be streamlined and reordered. Uppercase letters will be eliminated. They will issue a royal decree in the form of a String of B and A characters. The first character in the decree specifies whether a must come ( B )Before b in the new alphabet or ( A )After b . The second character determines the relative placement of b and c , etc. So, for example, "BAA" means that a must come Before b , b must come After c , and c must come After d . Any letters beyond these requirements are to be excluded, so if the decree specifies k comparisons then the new alphabet will contain the first k+1 lowercase letters of the current alphabet. Create a class Alphabet that contains the method choices that takes the decree as input and returns the number of possible new alphabets that conform to the decree. If more than 1,000,000,000 are possible, return -1. Definition
标签： government streamline important alphabet
上传时间： 2015-06-08
上传用户：weixiao99
FPGA Architecture: Survey and Challenges Ian Kuon1, Russell Tessier2 and Jonathan Rose1 1 The Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada, {ikuon, jayar}@eecg.utoronto.ca 2 Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA, USA, tessier@ecs.umass.edu
标签： Architecture Challenges and Jonathan
上传时间： 2013-11-25
上传用户：yuchunhai1990
Beamforming thesis describing Study of a various Beamforming Techniques And Implementation of the Constrained Least Mean Squares (LMS) algorithm for Beamforming
标签： Beamforming Implementation describing Techniques
上传时间： 2013-12-25
上传用户：wuyuying
