清单1 LSDAA: ADC R16,R16 ;十进制数（在R16中）左移调整子程序 ADDAA: IN R6,SREG ;bcd码相加调整子程序，先保存相加后的 LDI R17,$66 ;状态the old status ADD R16,R17 ;再将和预加立即数$66 IN R17,SREG ;输入相加后新状态(the new status) OR R6,R17 ;新旧状态相或 SBRS R6,0 ;相或后进位置位则跳行 SUBI R16,$60 ;否则减去$60(十位bcd不满足调整条件) SBRS R6,5 ;半进位置位则跳行 SUBI R16,6 ;否则减去$06(个位bcd不满足调整条件) ROR R6 ;向高位BCD返还进位位! RET
上传时间： 2013-10-07
上传用户：zh_901
Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective solution. Maxim's 3GPP TS25.104-compliant transceiver solution is presented along withcomplete radio reference designs such as RD2550. For more information on the RD2550, see reference design 5364, "FemtocellRadio Reference Designs Using the MAX2550–MAX2553 Transceivers."
标签： Base-Station Applications Single-Chip Transceiver
上传时间： 2013-11-06
上传用户：songrui
This application note describes how to retrieve user-defined data from Xilinx configurationPROMs (XC18V00 and Platform Flash devices) after the same PROM has configured theFPGA. The method to add user-defined data to the configuration PROM file is also discussed.The reference design described in this application note can be used in any of the followingXilinx FPGA architectures: Spartan™-II, Spartan-IIE, Spartan-3, Virtex™, Virtex-E, Virtex-II,and Virtex-II Pro.
上传时间： 2013-11-11
上传用户：zhouli
With the Altera Nios II embedded processor, you as the system designercan accelerate time-critical software algorithms by adding custominstructions to the Nios II processor instruction set. Using custominstructions, you can reduce a complex sequence of standard instructionsto a single instruction implemented in hardware. You can use this featurefor a variety of applications, for example, to optimize software innerloops for digital signal processing (DSP), packet header processing, andcomputation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphicaluser interface (GUI) used to add up to 256 custom instructions to theNios II processor
上传时间： 2013-11-06
上传用户：swing
Nios II定制指令用户指南：With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom instructions, you can reduce a complex sequence of standard instructions to a single instruction implemented in hardware. You can use this feature for a variety of applications, for example, to optimize software inner loops for digital signal processing (DSP), packet header processing, and computation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphical user interface (GUI) used to add up to 256 custom instructions to the Nios II processor. The custom instruction logic connects directly to the Nios II arithmetic logic unit (ALU) as shown in Figure 1–1.
上传时间： 2013-10-11
上传用户：kang1923
Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective solution. Maxim's 3GPP TS25.104-compliant transceiver solution is presented along withcomplete radio reference designs such as RD2550. For more information on the RD2550, see reference design 5364, "FemtocellRadio Reference Designs Using the MAX2550–MAX2553 Transceivers."
标签： Base-Station Applications Single-Chip Transceiver
上传时间： 2013-11-04
上传用户：超凡大师
This application note describes how to retrieve user-defined data from Xilinx configurationPROMs (XC18V00 and Platform Flash devices) after the same PROM has configured theFPGA. The method to add user-defined data to the configuration PROM file is also discussed.The reference design described in this application note can be used in any of the followingXilinx FPGA architectures: Spartan™-II, Spartan-IIE, Spartan-3, Virtex™, Virtex-E, Virtex-II,and Virtex-II Pro.
上传时间： 2013-10-08
上传用户：guojin_0704
如果用户现有的是 Protel99SE 。ProtelDXP，Protel2004 版本： 1 在powerpcb 软件的中打开 PCB 文件，选择导出 ASCII 文件（export ascii file） ，ascii file 的版本应该选择 3.5 及以下的版本。 2 a 在 Protel99SE 。ProtelDXP ， 选择 File->Import->在出现的对话框中,选择文件类型中的PADS Ascil Files (*.ASC)输入对应文件即可 1.powerpcb-->export ascii file--->import ascii file with protel99 se sp5(u must install padsimportor that is an add-on for 99sesp5 which can downloan from protel company ). 2.powerpcb-->export ascii file-->import ascii file in orcad layout-->import max file(orcad pcb file)with protel 99 or 99se.
上传时间： 2013-10-15
上传用户：whymatalab
本程序集是Allen I. Holub所写的《Compiler Design in C》一书的附随软件，其中有作者自己编写的词法分析和语法分析工具LeX，occs和LLama，该软件包还包括一个显示C语言分析过程的程序
上传时间： 2014-01-08
上传用户：siguazgb
PGP Components使用PGP算法的加密控件。(有源代码）工作在：D2 D3 D4 D5。作者：Michael in der Wiesche
标签： Components PGP Michael Wiesche
上传时间： 2013-12-28
上传用户：koulian
