搜索：datapath
找到约 8 项符合「datapath」的查询结果
结果 8
https://www.eeworm.com/dl/663/457174.html
VHDL/FPGA/Verilog
vhdl source code for 8 bit datapath logic
vhdl source code for 8 bit datapath logic
https://www.eeworm.com/dl/682/216942.html
中间件编程
 The purpose of this lab is to introduce the concept of FSMs with a datapath, and to stud
&#65279 The purpose of this lab is to introduce the concept of FSMs with a datapath, and to
study the usage of more complex test benches. Also, we enforce a rudimentary design
methodology by assuming that the students are part of a bigger project, and have no
knowledge o ...
https://www.eeworm.com/dl/663/406095.html
VHDL/FPGA/Verilog
for FPGA IMPLEMENTATION,OUR DATAPATH CREATED FOR TWO BIRS MULTIPLICATION
for FPGA IMPLEMENTATION,OUR DATAPATH CREATED FOR TWO BIRS MULTIPLICATION
https://www.eeworm.com/dl/663/450543.html
VHDL/FPGA/Verilog
datapath_fifo used in DMA contect PCI in the DAB system the format of this file is VHDL
datapath_fifo used in DMA contect PCI in the DAB system the format of this file is VHDL
https://www.eeworm.com/dl/534/430912.html
其他
This is a simple MIPS processor datapath written in VERILOG hardware language. You can see the signa
This is a simple MIPS processor datapath written in VERILOG hardware language. You can see the signals when emulating in signalscan. Compile it with verilog in linux.
https://www.eeworm.com/dl/647/183929.html
嵌入式/单片机编程
verilog程序
verilog程序，实现两个16bit数乘法，采用booth算法，基于状态机实现，分层次为datapath和controller两个子模块，testBench测试通过
https://www.eeworm.com/dl/663/442622.html
VHDL/FPGA/Verilog
这个设计是使用Virtex-4实现DDR的控制器的
这个设计是使用Virtex-4实现DDR的控制器的，设计分为三个主要模块：Front-End FIFOs,DDR SDRAM Controller和Datapath Module。其中主要是DDR SDRAM Controller,当然还有测试模块。
https://www.eeworm.com/dl/527/465363.html
通讯/手机编程
高速DDR存储器数据接口设计实例. 1. 将文件拷入硬盘 2. 产生DQS模块 3. 产生DQ模块 4. 产生PLL模块 5. 拷贝以上步骤生成的文件到子目录【Project】中 6. 打
高速DDR存储器数据接口设计实例.
1. 将文件拷入硬盘
2. 产生DQS模块
3. 产生DQ模块
4. 产生PLL模块
5. 拷贝以上步骤生成的文件到子目录【Project】中
6. 打开子目录【Project】中的DataPath.qpf工程，设计顶层模块
7. 编译并查看编译结果 ...