代码搜索：write_enable
找到约 99 项符合「write_enable」的源代码
代码结果 99
www.eeworm.com/read/154079/5642934
vhd stack.vhd
library LIB;
use LIB.SYNOPSYS.all;
use LIB.AMD_PACK.all;
entity STACK is
port(OPERATION : in STACK_OPS;
VALUE : in ADDRESS;
CLOCK : in BIT;
OUTPU
www.eeworm.com/read/439407/6932054
vhd tb_cam_ramb4.vhd
--
-- Module: TB_CAM_RAMB4
-- Design: Test Bench for CAM_RAMB4
-- VHDL code: Test vectors
-- Instantiate CAM_RAMB4
--
-- Simulation ModelSim EE v5.2e
--
-- Description: Read mode
-- Wri
www.eeworm.com/read/215970/15031632
tf fifoctrl_ic_tb1_timing.tf
/**********************************************************************\
* *
* Module : fifoctrl_ic_tb1.v Last up
www.eeworm.com/read/215970/15031648
tf fifoctrl_ic_tb1.tf
/**********************************************************************\
* *
* Module : fifoctrl_ic_tb1.v Last up
www.eeworm.com/read/439407/6932052
vhd cam_top.vhd
--
-- Module: CAM_Top / Top Level
-- Design: CAM_Top
-- VHDL code: Hierarchical wrapper
-- Instantiate CAM_generic_8s (depth variable by 16x8bits word)
--
-- Synthesis Synopsys FPGA Express v
www.eeworm.com/read/215970/15031635
tf fifoctrl_ic_tb2.tf
/**********************************************************************\
* *
* Module : fifoctrl_ic_tb2.v Last up
www.eeworm.com/read/215970/15031637
tf fifoctrl_ic_tb2_timing.tf
/**********************************************************************\
* *
* Module : fifoctrl_ic_tb2.v Last up
www.eeworm.com/read/9549/170090
v data_memory.v
module data_memory(clk, read_addr, out, write_enable, write_addr, write_value); //it's a ram
inout clk;
input[31:0] read_addr;
output reg[31:0] out;
input write_enable;
input[31:0] write_ad
www.eeworm.com/read/273082/10928439
v wr_cntrl_w.v
//////////////////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.2.34 Oct. 7, 2003
// Wed Mar 10 16:55:06 2004
//
//
www.eeworm.com/read/328513/13023727
v wr_cntrl_w.v
//////////////////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.2.34 Oct. 7, 2003
// Wed Mar 10 16:55:06 2004
//
//