代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/470983/6902393
vhd clk_1hz.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clk_1hz is
port(
clk10k:in std_logic; ------时钟信号10khZ
clk1hz:out std_logic); -----频率信号输出1Hz
www.eeworm.com/read/470420/6910461
vhd putin.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY PUTIN IS
PORT(CP0,CP1:IN STD_LOGIC;
DATA:IN STD_LOGIC_VECTOR
www.eeworm.com/read/470420/6910590
vhd show.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SHOW IS
PORT( SI:IN STD_LOGIC_VECTOR(4 DOWNTO 0);
SOU:OUT STD_LOGIC_VECTOR(4 downto 0));
end SHOW;
ARCHITECTURE PART1 OF SHOW IS
www.eeworm.com/read/470486/6911583
vhd liushuideng.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY liushuideng IS
PORT(
CLK: IN STD_LOGIC;
T:OUT STD_LOGIC_VECTOR(7 DOWNTO 0 )
);
END liushui
www.eeworm.com/read/470486/6911641
vhd liushuideng.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY liushuideng IS
PORT(
CLK: IN STD_LOGIC;
T:OUT STD_LOGIC_VECTOR(7 DOWNTO 0 )
);
END liushui
www.eeworm.com/read/470487/6911741
vhd 38.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY decorder38 IS
PORT(g1,g2a,g2b:in std_logic;
a,b,c:in std_logic;
y:out std_logic_vector(7 downto 0));
END decorder38;
ARC
www.eeworm.com/read/470487/6911754
vhd lsd.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY lsd IS
PORT(
CLK:IN STD_LOGIC;
Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END lsd;
ARCHITECTUR
www.eeworm.com/read/470487/6911770
vhd decorder38.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY decorder38 IS
PORT(g1,g2a,g2b:in std_logic;
a,b,c:in std_logic;
y:out std_logic_vector(7 downto 0));
END decorder38;
ARC
www.eeworm.com/read/470487/6911796
vhd deng.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY deng IS
PORT(
CLK:IN STD_LOGIC;
Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END deng;
ARCHITECT
www.eeworm.com/read/470487/6911825
vhd light.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY light IS
PORT(
CLK:IN STD_LOGIC;
Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END light;
ARCHITE