代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/416057/11043044
vhd shiftertestbench.vhd
--****************************************************************************************************
-- ARM barrel shifter testbench
-- Designed by Ruslan Lepetenok
--****************************
www.eeworm.com/read/416057/11043046
vhd dataoutmux.vhd
--****************************************************************************************************
-- Data out register for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 04.12.2002
--**
www.eeworm.com/read/416057/11043072
vhd psr.vhd
--****************************************************************************************************
-- Programm Status Registers for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 23.01.20
www.eeworm.com/read/416057/11043102
vhd ipdr.vhd
--****************************************************************************************************
-- Instruction pipeline register, data in register for ARM7TDMI-S processor
-- Designed by Rus
www.eeworm.com/read/416057/11043107
vhd armshiftertesttop.vhd
--****************************************************************************************************
-- Shifter tester top entity for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 07.12.20
www.eeworm.com/read/416057/11043108
vhd resltbitmask.vhd
--****************************************************************************************************
-- This module cleares/sets bit 0 and clears 1 of ALU bus for ARM7TDMI-S processor
-- Designed
www.eeworm.com/read/470937/6902112
vhd fenpinpwm20m_10k.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenpinpwm20M_10k is
port(
clk:in std_logic; ------时钟信号20MhZ
fout:out std_logic); -----频率信号输
www.eeworm.com/read/470937/6902114
vhd fenpinadc0809.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenpinadc0809 is
port(
clk:in std_logic; ------时钟信号20MhZ
fout:out std_logic); -----频率信号输出500K
www.eeworm.com/read/470937/6902120
vhd qiankui.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity qiankui is
port(input: in std_logic_vector(11 downto 0); --输入信号
cl
www.eeworm.com/read/470943/6902181
vhd piso.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity PiSo is
port(clk : in std_logic;
clr : in std_logic;
din : in std_logic_vector(7 downto 0);