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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity altgxb_hssi_word_aligner is
generic(
channel_width : integer := 10;
align_pattern_length: integer := 10;
infiniband_inva
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity hcstratix_mac_out_internal is
generic(
operation_mode : string := "output_only";
dataa_width : integer := 36;
datab_
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity hcstratix_lcell_register is
generic(
synch_mode : string := "off";
register_cascade_mode: string := "off";
power_up
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lpm_fifo_dc is
generic(
lpm_type : string := "lpm_fifo_dc";
lpm_width : integer := 1;
lpm_widthu : inte
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lpm_clshift is
generic(
lpm_width : integer := 1;
lpm_widthdist : integer := 1;
lpm_shifttype : string := "LOGI
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_lcell_register is
generic(
synch_mode : string := "off";
register_cascade_mode: string := "off";
power_up
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_mac_out_internal is
generic(
operation_mode : string := "output_only";
dataa_width : integer := 36;
datab_
qep_data_bus.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
spusnoop.v
// Produced by /usr/class/ee272/bin/snoopgen from file s.in
// Remember to run Verilog with -x if any variables are subscripted
// 2 Clock phases: phi1 phi2
// Input, Verilog: decisions_b_s1, irsi
main.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Qua