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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity tri_bus is
generic(
width_datain : integer := 1;
width_dataout : integer := 1
);
port(
datain : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity oper_less_than is
generic(
width_a : integer := 6;
width_b : integer := 6;
sgate_representation: integer :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity oper_decoder is
generic(
width_i : integer := 6;
width_o : integer := 6
);
port(
i :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cyclone_lcell_register is
generic(
synch_mode : string := "off";
register_cascade_mode: string := "off";
power_up
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cyclone_asynch_io is
generic(
operation_mode : string := "input";
bus_hold : string := "false";
open_drain_outpu
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_lcell_register is
generic(
synch_mode : string := "off";
register_cascade_mode: string := "off";
power_up
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_mac_out_internal is
generic(
operation_mode : string := "output_only";
dataa_width : integer := 36;
datab_
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity altgxb_tx_core is
generic(
use_double_data_mode: string := "OFF";
use_fifo_mode : string := "ON";
transmit_protocol: s
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity altgxb_8b10b_encoder is
generic(
transmit_protocol: string := "NONE";
use_8b_10b_mode : string := "ON";
force_disparity_
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity altgxb_hssi_symbol_aligner is
generic(
channel_width : integer := 10;
align_pattern_length: integer := 10;
infiniband_in