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library verilog; use verilog.vl_types.all; entity altfp_mult is generic( width_exp : integer := 8; width_man : integer := 23; dedicated_multiplier_circuitry: st

library verilog; use verilog.vl_types.all; entity stratixgx_tx_core is generic( use_double_data_mode: string := "false"; use_fifo_mode : string := "true"; transmit_prot

library verilog; use verilog.vl_types.all; entity stratixgx_hssi_symbol_aligner is generic( channel_width : integer := 10; align_pattern_length: integer := 10; infiniband

library verilog; use verilog.vl_types.all; entity stratixgx_hssi_word_aligner is generic( channel_width : integer := 10; align_pattern_length: integer := 10; infiniband_i

library verilog; use verilog.vl_types.all; entity stratixgx_8b10b_encoder is generic( transmit_protocol: string := "none"; use_8b_10b_mode : string := "true"; force_dispa

library verilog; use verilog.vl_types.all; entity flex6k_io is generic( operation_mode : string := "input"; feedback_mode : string := "from_pin"; power_up : str

library verilog; use verilog.vl_types.all; entity flex10ke_lcell_register is generic( operation_mode : string := "normal"; packed_mode : string := "false"; clock_ena

library verilog; use verilog.vl_types.all; entity apexii_asynch_pterm is generic( operation_mode : string := "normal"; invert_pterm1_mode: string := "false" ); port(

library verilog; use verilog.vl_types.all; entity mercury_hssi_synchronizer is generic( channel_width : integer := 20 ); port( datain : in vl_logic_vector(19

library verilog; use verilog.vl_types.all; entity max_mcell_register is generic( operation_mode : string := "normal"; power_up : string := "low"; register_mode