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Verilog 的代码
assert_delta.vlib
// Accellera Standard V1.0 Open Verification Library (OVL).
// Accellera Copyright (c) 2005. All rights reserved.
`include "std_ovl_defines.h"
`module assert_delta (clk, reset_n, test_expr);
assert_no_underflow.vlib
// Accellera Standard V1.0 Open Verification Library (OVL).
// Accellera Copyright (c) 2005. All rights reserved.
`include "std_ovl_defines.h"
`module assert_no_underflow (clk, reset_n, test_ex
assert_decrement.vlib
// Accellera Standard V1.0 Open Verification Library (OVL).
// Accellera Copyright (c) 2005. All rights reserved.
`include "std_ovl_defines.h"
`module assert_decrement (clk, reset_n, test_expr)
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity apex20ke_lvds_transmitter is
generic(
channel_width : integer := 8
);
port(
clk0 : in vl_logic;
c
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity apex20ke_lvds_receiver is
generic(
channel_width : integer := 8
);
port(
deskewin : in vl_logic;
clk0
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_lcell_register is
generic(
synch_mode : string := "off";
register_cascade_mode: string := "off";
power_up
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_mac_out_internal is
generic(
operation_mode : string := "output_only";
dataa_width : integer := 36;
datab_wi
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity altcdr_tx is
generic(
number_of_channels: integer := 1;
deserialization_factor: integer := 3;
inclock_period : integer :=
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity altcdr_rx is
generic(
number_of_channels: integer := 1;
deserialization_factor: integer := 3;
inclock_period : integer :=
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity scfifo is
generic(
lpm_width : integer := 1;
lpm_widthu : integer := 1;
lpm_numwords : integer := 2;