代码搜索结果

ISIS SCHEMATIC DESCRIPTION FORMAT 6.1 ===================================== Design: E:\毕业设计资料\Proteus在MCS-51&ARM7系统中的应用百例\MCS-51 examples\Chapter 4\14 Switch Lamp\Switch Lamp.DSN Doc. no.: Re

// Verilog model created from schematic outs3.sch - Thu Dec 05 17:54:29 2002 `timescale 1ns / 1ps module outs3(inputs, outs); input [9:0] inputs; output [9:0] outs; wire XLXN_12; wire

// Verilog model created from schematic J:\eda\Xilinx\virtex2\data\drawing\ftce.sch - Thu Dec 05 17:54:30 2002 `timescale 1ns / 1ps module FTCE_MXILINX_cnt60(C, CE, CLR, T, Q); input C;

// Verilog model created from schematic outs3.sch - Thu Dec 05 17:54:29 2002 `timescale 1ns / 1ps module outs3(inputs, outs); input [9:0] inputs; output [9:0] outs; wire XLXN_12; wire

// Verilog model created from schematic J:\eda\Xilinx\virtex2\data\drawing\ftce.sch - Thu Dec 05 17:54:30 2002 `timescale 1ns / 1ps module FTCE_MXILINX_cnt60(C, CE, CLR, T, Q); input C;

SCHEMATIC START ; // created by map version F.28 on Thu Mar 27 15:51:54 2003 COMP "modb_out" LOCATE = SITE "B6" LEVEL 1; COMP "top2a_c" LOCATE = SITE "A4" LEVEL 1; COMP "modb_clk_pad" LOCATE

SCHEMATIC START ; // created by map version F.28 on Thu Mar 27 15:47:31 2003 COMP "modb_out" LOCATE = SITE "B6" LEVEL 1; COMP "top2a_c" LOCATE = SITE "A4" LEVEL 1; COMP "modb_clk_pad" LOCATE

SCHEMATIC START ; // created by map version F.28 on Thu Mar 27 15:41:30 2003 COMP "top2a_c" LOCATE = SITE "A4" LEVEL 1; COMP "modb_clk_pad" LOCATE = SITE "D7" LEVEL 1; COMP "moda_data" LOCATE

SCHEMATIC START ; // created by map version F.28 on Thu Mar 27 16:07:52 2003 COMP "top2a_c" LOCATE = SITE "A4" LEVEL 1; COMP "modb_clk_pad" LOCATE = SITE "D7" LEVEL 1; COMP "dll_rst" LOCATE =

|HEADER=Protel for Windows - Schematic Capture Ascii File Version 5.0|WEIGHT=1281 |RECORD=31|FONTIDCOUNT=5|SIZE1=10|FONTNAME1=Times New Roman|SIZE2=10|ROTATION2=90|FONTNAME2=Times New Roman|SIZE3=12|