代码搜索结果
找到约 2,625 项符合
Schematic 的代码
outs3.vf
// Verilog model created from schematic outs3.sch - Thu Dec 05 17:54:29 2002
`timescale 1ns / 1ps
module outs3(inputs, outs);
input [9:0] inputs;
output [9:0] outs;
wire XLXN_12;
wire
cnt60.vf
// Verilog model created from schematic J:\eda\Xilinx\virtex2\data\drawing\ftce.sch - Thu Dec 05 17:54:30 2002
`timescale 1ns / 1ps
module FTCE_MXILINX_cnt60(C, CE, CLR, T, Q);
input C;
outs3.vf
// Verilog model created from schematic outs3.sch - Thu Dec 05 17:54:29 2002
`timescale 1ns / 1ps
module outs3(inputs, outs);
input [9:0] inputs;
output [9:0] outs;
wire XLXN_12;
wire
cnt60.vf
// Verilog model created from schematic J:\eda\Xilinx\virtex2\data\drawing\ftce.sch - Thu Dec 05 17:54:30 2002
`timescale 1ns / 1ps
module FTCE_MXILINX_cnt60(C, CE, CLR, T, Q);
input C;
top.pcf
SCHEMATIC START ;
// created by map version F.28 on Thu Mar 27 15:51:54 2003
COMP "modb_out" LOCATE = SITE "B6" LEVEL 1;
COMP "top2a_c" LOCATE = SITE "A4" LEVEL 1;
COMP "modb_clk_pad" LOCATE
top.pcf
SCHEMATIC START ;
// created by map version F.28 on Thu Mar 27 15:47:31 2003
COMP "modb_out" LOCATE = SITE "B6" LEVEL 1;
COMP "top2a_c" LOCATE = SITE "A4" LEVEL 1;
COMP "modb_clk_pad" LOCATE
top.pcf
SCHEMATIC START ;
// created by map version F.28 on Thu Mar 27 15:41:30 2003
COMP "top2a_c" LOCATE = SITE "A4" LEVEL 1;
COMP "modb_clk_pad" LOCATE = SITE "D7" LEVEL 1;
COMP "moda_data" LOCATE
top.pcf
SCHEMATIC START ;
// created by map version F.28 on Thu Mar 27 16:07:52 2003
COMP "top2a_c" LOCATE = SITE "A4" LEVEL 1;
COMP "modb_clk_pad" LOCATE = SITE "D7" LEVEL 1;
COMP "dll_rst" LOCATE =
fpga_40rs232.pcf
SCHEMATIC START ;
// created by map version G.28 on Sun Feb 26 16:53:27 2006
COMP "reset1" LOCATE = SITE "P163" LEVEL 1;
COMP "CTS" LOCATE = SITE "P127" LEVEL 1;
COMP "RD" LOCATE = SITE "P13
fpga_40rs232.pcf
SCHEMATIC START ;
// created by map version G.28 on Sun Feb 26 16:53:27 2006
COMP "reset1" LOCATE = SITE "P163" LEVEL 1;
COMP "CTS" LOCATE = SITE "P127" LEVEL 1;
COMP "RD" LOCATE = SITE "P13