代码搜索结果

[project] name=pa netlist=pa contents=pa date=02/07/01 time=15:42:22 version=3.1.6.00.09 generics=MAX Type=F21i FndType=F3.1i top_level=schematic lib_order=1008 133 169 library_net=ON [li

SCHEMATIC START ; // created by map version G.28 on Tue Dec 05 11:55:45 2006 COMP "addr_SRAM" LOCATE = SITE "P203" LEVEL 1; COMP "addr_SRAM" LOCATE = SITE "P200" LEVEL 1; COMP "addr_SRA

SCHEMATIC START ; // created by map version G.28 on Fri Dec 15 10:35:27 2006 COMP "addr_SRAM" LOCATE = SITE "P203" LEVEL 1; COMP "addr_SRAM" LOCATE = SITE "P200" LEVEL 1; COMP "addr_SRA

SCHEMATIC START ; // created by map version G.28 on Fri Dec 15 10:43:41 2006 COMP "addr_SRAM" LOCATE = SITE "P203" LEVEL 1; COMP "addr_SRAM" LOCATE = SITE "P200" LEVEL 1; COMP "addr_SRA

SCHEMATIC START ; // created by map version E.35 on Tue Dec 17 10:05:37 2002 COMP "ck" LOCATE = SITE "P113" LEVEL 1; COMP "clk" LOCATE = SITE "P213" LEVEL 1; COMP "ck_x" LOCATE = SITE "P114" LE

// Verilog model created from schematic outs3.sch - Thu Dec 05 17:54:29 2002 `timescale 1ns / 1ps module outs3(inputs, outs); input [9:0] inputs; output [9:0] outs; wire XLXN_12; wire

// Verilog model created from schematic J:\eda\Xilinx\virtex2\data\drawing\ftce.sch - Thu Dec 05 17:54:30 2002 `timescale 1ns / 1ps module FTCE_MXILINX_cnt60(C, CE, CLR, T, Q); input C;

// Verilog model created from schematic outs3.sch - Thu Dec 05 17:54:29 2002 `timescale 1ns / 1ps module outs3(inputs, outs); input [9:0] inputs; output [9:0] outs; wire XLXN_12; wire

// Verilog model created from schematic J:\eda\Xilinx\virtex2\data\drawing\ftce.sch - Thu Dec 05 17:54:30 2002 `timescale 1ns / 1ps module FTCE_MXILINX_cnt60(C, CE, CLR, T, Q); input C;

SCHEMATIC START ; // created by map version F.28 on Thu Mar 27 15:51:54 2003 COMP "modb_out" LOCATE = SITE "B6" LEVEL 1; COMP "top2a_c" LOCATE = SITE "A4" LEVEL 1; COMP "modb_clk_pad" LOCATE