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module ad7301_ctrl(reset, LCLK, sample_start, SCLK,//shu chu ad xin pian dang zhong DOUT,//cong ad xin pian zhong hui du,shu ru dao FPGA zhong //ad7301_CS_,//shu ch

-- State Machine with Asynchronous Reset -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity stmch1 is port(clk, in1, rst: in std_logic;

// RS-232 example // Compiles with Microsoft Visual C++ 5.0/6.0 // (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005, 2006 #include #include #include HANDLE hCom;

// sync SCK to the FPGA clock using a 3-bits shift register reg [2:0] SCKr; always @(posedge clk) SCKr

-- TTL164 Shift Register -- download from: www.fpga.com.cn & www.pld.com.cn library IEEE; use IEEE.Std_logic_1164.all; ENTITY dev164 IS PORT(a, b, nclr, clock : IN BIT; q : BUFFE

-- Classic 2-Process State Machine and Test Bench -- MEALY TYPE STATE MACHINE EXAMPLE -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; ENTITY fsm I

-- State Machine with Asynchronous Reset -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity stmch1 is port(clk, in1, rst: in std_logic;

-- Dual 2-to-4 Decoder -- A set of conditional signal assignments model a dual 2-to-4 decoder -- uses 1993 std VHDL -- download from: www.pld.com.cn & www.fpga.com.cn library IEEE; use IEEE.Std

-- Octal D-Type Register with 3-State Outputs -- Simple model of an Octal D-type register with three-state outputs using two concurrent statements. -- download from: www.fpga.com.cn & www.pld.com.cn

-- TTL164 Shift Register -- download from: www.fpga.com.cn & www.pld.com.cn library IEEE; use IEEE.Std_logic_1164.all; ENTITY dev164 IS PORT(a, b, nclr, clock : IN BIT; q : BUFFE