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-- Classic 2-Process State Machine and Test Bench -- MEALY TYPE STATE MACHINE EXAMPLE -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; ENTITY fsm I

-- Octal D-Type Register with 3-State Outputs -- Simple model of an Octal D-type register with three-state outputs using two concurrent statements. -- download from: www.fpga.com.cn & www.pld.com.cn

-- Dual 2-to-4 Decoder -- A set of conditional signal assignments model a dual 2-to-4 decoder -- uses 1993 std VHDL -- download from: www.pld.com.cn & www.fpga.com.cn library IEEE; use IEEE.Std

#include "FPGA_Test.h" //SPORT0 Setup void Init_SPORTS0(void) { //MSB first External TCLK/RCLK External FRAME // configure SPORT0 receiver and transmitter 16-bit transfer *pSPORT0_RCR1 =

-- Dual 2-to-4 Decoder -- A set of conditional signal assignments model a dual 2-to-4 decoder -- uses 1993 std VHDL -- download from: www.pld.com.cn & www.fpga.com.cn library IEEE; use IEEE.Std

#Build: Synplify Pro 9.0.1, Build 024R, Nov 13 2007 #install: C:\Program Files\Synplicity\fpga_901 #OS: Windows XP 5.1 #Hostname: QIN #Implementation: rev_1 #Sat Jul 19 16:07:05 2008 $ Sta

#Build: Synplify Pro 9.0.1, Build 024R, Nov 13 2007 #install: C:\Program Files\Synplicity\fpga_901 #OS: Windows XP 5.1 #Hostname: QIN #Implementation: rev_1 #Sat Jul 19 16:07:05 2008 $ Sta

-- Dual 2-to-4 Decoder -- A set of conditional signal assignments model a dual 2-to-4 decoder -- uses 1993 std VHDL -- download from: www.pld.com.cn & www.fpga.com.cn library IEEE; use IEEE.Std

Release 7.1.01i Map H.39 Xilinx Mapping Report File for Design 'electronic_organ' Design Information ------------------ Command Line : E:/Program/EDA/Xilinx/bin/nt/map.exe -ise e:\demo_fpga\DEMO_F

/* Netlist to be placed stuff. */ int num_nets, num_blocks; struct s_net *net; struct s_block *block; boolean *is_global; /* Physical FPGA architecture stuff */ int nx, ny; /* chan_width_x is the x-