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FPGA 的代码
带同步复位的状态机.txt
-- State Machine with Asynchronous Reset
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity stmch1 is
port(clk, in1, rst: in std_logic;
双2－4译码器：74139.txt
-- Dual 2-to-4 Decoder
-- A set of conditional signal assignments model a dual 2-to-4 decoder
-- uses 1993 std VHDL
-- download from: www.pld.com.cn & www.fpga.com.cn
library IEEE;
use IEEE.Std
带三态输出的8位d寄存器：74374.txt
-- Octal D-Type Register with 3-State Outputs
-- Simple model of an Octal D-type register with three-state outputs using two concurrent statements.
-- download from: www.fpga.com.cn & www.pld.com.cn
dev_c6sup1_mpfpga.c
/*
* Cisco router simulation platform.
* Copyright (c) 2007 Christophe Fillot (cf@utc.fr)
*
* C6k-Sup1a Midplane FPGA.
*/
#include
#include
#include
#include "c
dev_c7200_mpfpga.h
/*
* Cisco router simulation platform.
* Copyright (c) 2005-2007 Christophe Fillot (cf@utc.fr)
*
* Cisco c7200 Midplane FPGA.
*/
#ifndef __DEV_C7200_MPFPGA_H__
#define __DEV_C7200_MPFPGA_H__
/
com.c
// RS-232 example
// Compiles with Microsoft Visual C++ 5.0/6.0
// (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005, 2006
#include
#include
#include
HANDLE hCom;
readme
This directory includes ....
1. smarti.v : usb to smartmedia card interface .
2. smarti_box.v : smart box for fpga synthesis .
3. smarti_params.v : parameters.
4. tri_bus.v : bidirectional i
state_areset.txt
-- State Machine with Asynchronous Reset
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity stmch1 is
port(clk, in1, rst: in std_logic;
register_374.txt
-- Octal D-Type Register with 3-State Outputs
-- Simple model of an Octal D-type register with three-state outputs using two concurrent statements.
-- download from: www.fpga.com.cn & www.pld.com.cn
shift_register_164.txt
-- TTL164 Shift Register
-- download from: www.fpga.com.cn & www.pld.com.cn
library IEEE;
use IEEE.Std_logic_1164.all;
ENTITY dev164 IS
PORT(a, b, nclr, clock : IN BIT;
q : BUFFE