代码搜索结果
找到约 10,000 项符合
Clock 的代码
clock.asm.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
clock.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
clock.hier_info
|clock
set => trs38:U1.clk
date => noce.IN1
date => smin.IN1
date => shour.IN1
date => sday.IN1
date => smon.IN1
date => scmin.IN1
date => schour.IN1
date => process2~3.IN1
clo => cecl.IN1
clock_gen.v
// Clock_Gen.v
/****************为LCD_Drvier模块产生500Hz的时钟信号**************/
module Clock_Gen(clk_48M,rst,clk_LCD);
input clk_48M,rst; //rst为全局复位信号（高电平有效）
output cl
posix_clock.c
/****************************************************************************/
/* Function: taskDelay and POSIX RT clock demonstration */
/*
fm_clock.m
function fm_clock(varargin)
% FM_CLOCK create a clock
%
%Author: Federico Milano
%Date: 11-Nov-2002
%Update: 10-Feb-2003
%Version: 1.0.2
%
%E-mail: fmilano@thunderbox.uwaterloo
chess_clock.txt
-- Chess Clock
-- some expressions can not be synthetized,only for Simulation. (such as "AFTER 500 ms")
-- download from: www.fpga.com.cn & www.pld.com.cn
PACKAGE chesspack IS
SUBTYPE hour