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📄 clock.rpt

📁 1．6个数码管静态显示驱动 2．按键模式选择(时分秒)与调整控制 3．用硬件描述语言(或混合原理图)设计时、分、秒计数器模块、按键控制状态机模块、显示译码模块、顶层模块。要求使用实验箱右下角的6个
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B:       7/144(  4%)    13/ 72( 18%)     0/ 72(  0%)    0/16(  0%)      6/16( 37%)     0/16(  0%)
C:       3/144(  2%)     8/ 72( 11%)     0/ 72(  0%)    0/16(  0%)      6/16( 37%)     0/16(  0%)
D:      14/144(  9%)    12/ 72( 16%)     7/ 72(  9%)    0/16(  0%)      9/16( 56%)     0/16(  0%)
E:       1/144(  0%)     0/ 72(  0%)     0/ 72(  0%)    0/16(  0%)      1/16(  6%)     0/16(  0%)
F:       0/144(  0%)     0/ 72(  0%)     0/ 72(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      3/24( 12%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      2/24(  8%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      2/24(  8%)     0/4(  0%)      2/4( 50%)       0/4(  0%)
05:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
06:      2/24(  8%)     0/4(  0%)      2/4( 50%)       0/4(  0%)
07:      4/24( 16%)     0/4(  0%)      2/4( 50%)       0/4(  0%)
08:      3/24( 12%)     0/4(  0%)      2/4( 50%)       0/4(  0%)
09:      3/24( 12%)     0/4(  0%)      3/4( 75%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      2/24(  8%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
21:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
22:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
23:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
24:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
25:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
26:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
27:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
28:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
29:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
30:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
31:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
32:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
33:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
34:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
35:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
36:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                                 g:\top1\clock.rpt
clock

** CLOCK SIGNALS **

Type     Fan-out       Name
LCELL        9         |mode_adjust:G1|:725
LCELL        9         |mode_adjust:G1|:731
LCELL        9         |mode_adjust:G1|:737
INPUT        2         mode


Device-Specific Information:                                 g:\top1\clock.rpt
clock

** EQUATIONS **

adjust   : INPUT;
clk1HZ   : INPUT;
clk2HZ   : INPUT;
mode     : INPUT;
reset    : INPUT;
vcc      : INPUT;

-- Node name is 'cout24' 
-- Equation name is 'cout24', type is output 
cout24   =  _LC2_D26;

-- Node name is 'en0' 
-- Equation name is 'en0', type is output 
en0      =  _LC1_B10;

-- Node name is 'en1' 
-- Equation name is 'en1', type is output 
en1      =  _LC4_B10;

-- Node name is 'en2' 
-- Equation name is 'en2', type is output 
en2      =  _LC4_B8;

-- Node name is 'en3' 
-- Equation name is 'en3', type is output 
en3      =  _LC8_B8;

-- Node name is 'en4' 
-- Equation name is 'en4', type is output 
en4      =  _LC3_B3;

-- Node name is 'en5' 
-- Equation name is 'en5', type is output 
en5      =  _LC2_B3;

-- Node name is 'hh0' 
-- Equation name is 'hh0', type is output 
hh0      =  _LC4_D4;

-- Node name is 'hh1' 
-- Equation name is 'hh1', type is output 
hh1      =  _LC8_D5;

-- Node name is 'hh2' 
-- Equation name is 'hh2', type is output 
hh2      =  _LC5_D6;

-- Node name is 'hh3' 
-- Equation name is 'hh3', type is output 
hh3      =  _LC6_D6;

-- Node name is 'hh4' 
-- Equation name is 'hh4', type is output 
hh4      =  _LC2_D8;

-- Node name is 'hh5' 
-- Equation name is 'hh5', type is output 
hh5      =  _LC1_D8;

-- Node name is 'hh6' 
-- Equation name is 'hh6', type is output 
hh6      =  _LC2_D10;

-- Node name is 'hl0' 
-- Equation name is 'hl0', type is output 
hl0      =  _LC4_D22;

-- Node name is 'hl1' 
-- Equation name is 'hl1', type is output 
hl1      =  _LC1_D22;

-- Node name is 'hl2' 
-- Equation name is 'hl2', type is output 
hl2      =  _LC2_D22;

-- Node name is 'hl3' 
-- Equation name is 'hl3', type is output 
hl3      =  _LC3_D22;

-- Node name is 'hl4' 
-- Equation name is 'hl4', type is output 
hl4      =  _LC8_D22;

-- Node name is 'hl5' 
-- Equation name is 'hl5', type is output 
hl5      =  _LC5_D22;

-- Node name is 'hl6' 
-- Equation name is 'hl6', type is output 
hl6      =  _LC6_D22;

-- Node name is 'mh0' 
-- Equation name is 'mh0', type is output 
mh0      =  _LC5_B2;

-- Node name is 'mh1' 
-- Equation name is 'mh1', type is output 
mh1      =  _LC8_B2;

-- Node name is 'mh2' 
-- Equation name is 'mh2', type is output 
mh2      =  _LC1_B1;

-- Node name is 'mh3' 
-- Equation name is 'mh3', type is output 
mh3      =  _LC2_B6;

-- Node name is 'ml0' 
-- Equation name is 'ml0', type is output 
ml0      =  _LC3_B6;

-- Node name is 'ml1' 
-- Equation name is 'ml1', type is output 
ml1      =  _LC5_B6;

-- Node name is 'ml2' 
-- Equation name is 'ml2', type is output 
ml2      =  _LC6_B6;

-- Node name is 'ml3' 
-- Equation name is 'ml3', type is output 
ml3      =  _LC7_B6;

-- Node name is 'sh0' 
-- Equation name is 'sh0', type is output 
sh0      =  _LC1_C3;

-- Node name is 'sh1' 
-- Equation name is 'sh1', type is output 
sh1      =  _LC3_C16;

-- Node name is 'sh2' 
-- Equation name is 'sh2', type is output 
sh2      =  _LC4_C16;

-- Node name is 'sh3' 
-- Equation name is 'sh3', type is output 
sh3      =  _LC8_C16;

-- Node name is 'sl0' 
-- Equation name is 'sl0', type is output 
sl0      =  _LC6_C7;

-- Node name is 'sl1' 
-- Equation name is 'sl1', type is output 
sl1      =  _LC8_C7;

-- Node name is 'sl2' 
-- Equation name is 'sl2', type is output 
sl2      =  _LC1_C7;

-- Node name is 'sl3' 
-- Equation name is 'sl3', type is output 
sl3      =  _LC3_C7;

-- Node name is '|count24:G2|LPM_ADD_SUB:115|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_D11', type is buried 
_LC5_D11 = LCELL( _EQ001);
  _EQ001 =  _LC1_D11 &  _LC6_D26;

-- Node name is '|count24:G2|LPM_ADD_SUB:144|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_D26', type is buried 
!_LC5_D26 = _LC5_D26~NOT;
_LC5_D26~NOT = LCELL( _EQ002);
  _EQ002 = !_LC2_D33
         # !_LC4_D26;

-- Node name is '|count24:G2|LPM_ADD_SUB:144|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_D26', type is buried 
_LC1_D26 = LCELL( _EQ003);
  _EQ003 =  _LC2_D33 &  _LC4_D26 &  _LC7_D26;

-- Node name is '|count24:G2|:15' = '|count24:G2|yh0' 
-- Equation name is '_LC6_D26', type is buried 
_LC6_D26 = DFFE( _EQ004,  _LC2_B1,  VCC,  VCC,  VCC);
  _EQ004 = !_LC2_B2 &  _LC6_D26
         # !_LC2_D26 &  _LC6_D26 & !_LC7_D22
         #  _LC2_B2 & !_LC2_D26 & !_LC6_D26 &  _LC7_D22;

-- Node name is '|count24:G2|:14' = '|count24:G2|yh1' 
-- Equation name is '_LC1_D11', type is buried 
_LC1_D11 = DFFE( _EQ005,  _LC2_B1,  VCC,  VCC,  VCC);
  _EQ005 =  _LC2_B2 & !_LC2_D26 &  _LC8_D11
         #  _LC1_D11 & !_LC2_B2;

-- Node name is '|count24:G2|:13' = '|count24:G2|yh2' 
-- Equation name is '_LC3_D11', type is buried 
_LC3_D11 = DFFE( _EQ006,  _LC2_B1,  VCC,  VCC,  VCC);
  _EQ006 = !_LC2_B2 &  _LC3_D11
         #  _LC2_B2 & !_LC2_D26 &  _LC6_D11;

-- Node name is '|count24:G2|:12' = '|count24:G2|yh3' 
-- Equation name is '_LC2_D11', type is buried 
_LC2_D11 = DFFE( _EQ007,  _LC2_B1,  VCC,  VCC,  VCC);
  _EQ007 =  _LC2_B2 & !_LC2_D26 &  _LC7_D11
         # !_LC2_B2 &  _LC2_D11;

-- Node name is '|count24:G2|:19' = '|count24:G2|yl0' 
-- Equation name is '_LC2_D33', type is buried 
_LC2_D33 = DFFE( _EQ008,  _LC2_B1,  VCC,  VCC,  VCC);
  _EQ008 = !_LC2_B2 &  _LC2_D33
         #  _LC2_B2 & !_LC2_D33;

-- Node name is '|count24:G2|:18' = '|count24:G2|yl1' 
-- Equation name is '_LC4_D26', type is buried 
_LC4_D26 = DFFE( _EQ009,  _LC2_B1,  VCC,  VCC,  VCC);
  _EQ009 =  _LC2_D33 & !_LC4_D26 &  _LC8_D26
         # !_LC2_D33 &  _LC4_D26 &  _LC8_D26
         # !_LC2_B2 &  _LC4_D26;
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