📄 clock.rpt
字号:
B3 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
B6 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 3/22( 13%)
B8 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 1/2 0/2 3/22( 13%)
B10 3/ 8( 37%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
C3 3/ 8( 37%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 7/22( 31%)
C7 7/ 8( 87%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 2/22( 9%)
C16 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 0/2 5/22( 22%)
D4 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
D5 8/ 8(100%) 1/ 8( 12%) 7/ 8( 87%) 0/2 0/2 4/22( 18%)
D6 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 6/22( 27%)
D8 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 6/22( 27%)
D10 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
D11 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
D22 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 4/22( 18%)
D26 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 5/22( 22%)
D33 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 0/6 ( 0%)
Total I/O pins used: 43/141 ( 30%)
Total logic cells used: 94/1728 ( 5%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.59/4 ( 89%)
Total fan-in: 338/6912 ( 4%)
Total input pins required: 6
Total input I/O cell registers required: 0
Total output pins required: 37
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 94
Total flipflops required: 26
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 6/1728 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 8 8 2 0 0 8 0 8 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37/0
C: 0 0 3 0 0 0 7 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18/0
D: 0 0 0 1 8 2 0 2 0 1 8 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 8 0 0 0 0 0 0 1 0 0 0 39/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 8 8 5 1 8 10 7 10 0 4 8 0 0 0 0 8 0 0 0 0 0 0 8 0 0 0 8 0 0 0 0 0 0 1 0 0 0 94/0
Device-Specific Information: g:\top1\clock.rpt
clock
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
69 - - - 23 INPUT ^ 0 0 0 3 adjust
70 - - - 22 INPUT ^ 0 0 0 3 clk1HZ
71 - - - 21 INPUT ^ 0 0 0 6 clk2HZ
68 - - - 24 INPUT ^ 0 0 0 2 mode
173 - - - 13 INPUT ^ 0 0 0 13 reset
187 - - - 20 INPUT ^ 0 0 0 8 vcc
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: g:\top1\clock.rpt
clock
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
193 - - - 25 OUTPUT 0 1 0 0 cout24
94 - - - 09 OUTPUT 0 1 0 0 en0
95 - - - 09 OUTPUT 0 1 0 0 en1
96 - - - 08 OUTPUT 0 1 0 0 en2
97 - - - 07 OUTPUT 0 1 0 0 en3
37 - - E -- OUTPUT 0 1 0 0 en4
160 - - - 04 OUTPUT 0 1 0 0 en5
161 - - - 04 OUTPUT 0 1 0 0 hh0
162 - - - 05 OUTPUT 0 1 0 0 hh1
163 - - - 06 OUTPUT 0 1 0 0 hh2
164 - - - 06 OUTPUT 0 1 0 0 hh3
166 - - - 07 OUTPUT 0 1 0 0 hh4
167 - - - 08 OUTPUT 0 1 0 0 hh5
168 - - - 09 OUTPUT 0 1 0 0 hh6
25 - - D -- OUTPUT 0 1 0 0 hl0
26 - - D -- OUTPUT 0 1 0 0 hl1
27 - - D -- OUTPUT 0 1 0 0 hl2
28 - - D -- OUTPUT 0 1 0 0 hl3
29 - - D -- OUTPUT 0 1 0 0 hl4
30 - - D -- OUTPUT 0 1 0 0 hl5
31 - - D -- OUTPUT 0 1 0 0 hl6
148 - - A -- OUTPUT 0 1 0 0 mh0
147 - - A -- OUTPUT 0 1 0 0 mh1
144 - - B -- OUTPUT 0 1 0 0 mh2
143 - - B -- OUTPUT 0 1 0 0 mh3
142 - - B -- OUTPUT 0 1 0 0 ml0
141 - - B -- OUTPUT 0 1 0 0 ml1
140 - - B -- OUTPUT 0 1 0 0 ml2
139 - - B -- OUTPUT 0 1 0 0 ml3
136 - - C -- OUTPUT 0 1 0 0 sh0
135 - - C -- OUTPUT 0 1 0 0 sh1
134 - - C -- OUTPUT 0 1 0 0 sh2
133 - - C -- OUTPUT 0 1 0 0 sh3
132 - - C -- OUTPUT 0 1 0 0 sl0
131 - - C -- OUTPUT 0 1 0 0 sl1
128 - - D -- OUTPUT 0 1 0 0 sl2
127 - - D -- OUTPUT 0 1 0 0 sl3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: g:\top1\clock.rpt
clock
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - D 11 AND2 0 2 0 3 |count24:G2|LPM_ADD_SUB:115|addcore:adder|:55
- 5 - D 26 OR2 ! 0 2 0 2 |count24:G2|LPM_ADD_SUB:144|addcore:adder|:55
- 1 - D 26 AND2 0 3 0 1 |count24:G2|LPM_ADD_SUB:144|addcore:adder|:59
- 2 - D 11 DFFE 0 4 0 11 |count24:G2|yh3 (|count24:G2|:12)
- 3 - D 11 DFFE 0 4 0 12 |count24:G2|yh2 (|count24:G2|:13)
- 1 - D 11 DFFE 0 4 0 11 |count24:G2|yh1 (|count24:G2|:14)
- 6 - D 26 DFFE 0 4 0 11 |count24:G2|yh0 (|count24:G2|:15)
- 3 - D 26 DFFE 0 4 0 9 |count24:G2|yl3 (|count24:G2|:16)
- 7 - D 26 DFFE 0 4 0 10 |count24:G2|yl2 (|count24:G2|:17)
- 4 - D 26 DFFE 0 4 0 10 |count24:G2|yl1 (|count24:G2|:18)
- 2 - D 33 DFFE 0 2 0 11 |count24:G2|yl0 (|count24:G2|:19)
- 2 - D 26 OR2 ! 0 4 1 5 |count24:G2|:77
- 7 - D 22 OR2 ! 0 4 0 5 |count24:G2|:82
- 7 - D 11 OR2 0 4 0 1 |count24:G2|:162
- 6 - D 11 OR2 0 3 0 1 |count24:G2|:174
- 8 - D 11 OR2 0 3 0 1 |count24:G2|:183
- 8 - D 26 AND2 s 0 3 0 3 |count24:G2|~276~1
- 6 - B 02 AND2 0 2 0 1 |count60:G3|LPM_ADD_SUB:115|addcore:adder|:55
- 4 - B 06 AND2 0 2 0 1 |count60:G3|LPM_ADD_SUB:144|addcore:adder|:55
- 8 - B 06 AND2 0 3 0 1 |count60:G3|LPM_ADD_SUB:144|addcore:adder|:59
- 5 - B 02 DFFE 0 4 1 2 |count60:G3|yh3 (|count60:G3|:12)
- 8 - B 02 DFFE 0 4 1 3 |count60:G3|yh2 (|count60:G3|:13)
- 1 - B 01 DFFE 0 4 1 4 |count60:G3|yh1 (|count60:G3|:14)
- 2 - B 06 DFFE 0 4 1 5 |count60:G3|yh0 (|count60:G3|:15)
- 3 - B 06 DFFE 0 4 1 1 |count60:G3|yl3 (|count60:G3|:16)
- 5 - B 06 DFFE 0 4 1 2 |count60:G3|yl2 (|count60:G3|:17)
- 6 - B 06 DFFE 0 4 1 3 |count60:G3|yl1 (|count60:G3|:18)
- 7 - B 06 DFFE 0 2 1 4 |count60:G3|yl0 (|count60:G3|:19)
- 1 - B 02 OR2 s ! 0 4 0 2 |count60:G3|~77~1
- 1 - B 06 OR2 ! 0 4 0 8 |count60:G3|:82
- 7 - B 02 OR2 0 4 0 1 |count60:G3|:162
- 4 - B 02 OR2 0 4 0 1 |count60:G3|:174
- 8 - B 01 OR2 0 3 0 1 |count60:G3|:183
- 3 - B 02 OR2 s 0 3 0 4 |count60:G3|~252~1
- 2 - C 03 AND2 0 2 0 1 |count60:G4|LPM_ADD_SUB:115|addcore:adder|:55
- 2 - C 07 AND2 0 2 0 1 |count60:G4|LPM_ADD_SUB:144|addcore:adder|:55
- 4 - C 07 OR2 0 4 0 1 |count60:G4|LPM_ADD_SUB:144|addcore:adder|:69
- 1 - C 03 DFFE 1 3 1 2 |count60:G4|yh3 (|count60:G4|:12)
- 3 - C 16 DFFE 1 3 1 3 |count60:G4|yh2 (|count60:G4|:13)
- 4 - C 16 DFFE 1 3 1 4 |count60:G4|yh1 (|count60:G4|:14)
- 8 - C 16 DFFE 1 3 1 5 |count60:G4|yh0 (|count60:G4|:15)
- 6 - C 07 DFFE 1 3 1 2 |count60:G4|yl3 (|count60:G4|:16)
- 8 - C 07 DFFE 1 3 1 2 |count60:G4|yl2 (|count60:G4|:17)
- 1 - C 07 DFFE 1 3 1 3 |count60:G4|yl1 (|count60:G4|:18)
- 3 - C 07 DFFE 1 1 1 4 |count60:G4|yl0 (|count60:G4|:19)
- 5 - C 07 OR2 ! 0 4 0 9 |count60:G4|:82
- 3 - C 03 OR2 0 4 0 1 |count60:G4|:162
- 7 - C 16 OR2 0 4 0 1 |count60:G4|:174
- 5 - C 16 OR2 0 3 0 1 |count60:G4|:183
- 2 - C 16 OR2 s ! 0 3 0 2 |count60:G4|~395~1
- 1 - C 16 OR2 ! 0 3 0 5 |count60:G4|:395
- 2 - D 05 OR2 ! 0 4 0 4 |decode4_7:G5|:351
- 6 - D 05 AND2 0 4 0 5 |decode4_7:G5|:363
- 4 - D 11 OR2 s 0 4 0 3 |decode4_7:G5|~368~1
- 5 - D 05 AND2 0 4 0 5 |decode4_7:G5|:375
- 4 - D 04 OR2 0 4 1 0 |decode4_7:G5|:380
- 8 - D 05 OR2 0 4 1 0 |decode4_7:G5|:413
- 7 - D 05 OR2 0 4 0 1 |decode4_7:G5|:440
- 5 - D 06 OR2 0 4 1 0 |decode4_7:G5|:446
- 1 - D 05 OR2 0 4 0 1 |decode4_7:G5|:465
- 6 - D 06 OR2 0 4 1 0 |decode4_7:G5|:479
- 4 - D 05 OR2 0 4 0 1 |decode4_7:G5|:501
- 2 - D 08 OR2 0 4 1 0 |decode4_7:G5|:512
- 3 - D 05 OR2 0 4 0 2 |decode4_7:G5|:536
- 1 - D 08 OR2 0 4 1 0 |decode4_7:G5|:545
- 2 - D 10 OR2 0 4 1 0 |decode4_7:G5|:576
- 4 - D 22 OR2 0 4 1 0 |decode4_7:G6|:380
- 1 - D 22 OR2 0 4 1 0 |decode4_7:G6|:413
- 2 - D 22 OR2 0 4 1 0 |decode4_7:G6|:446
- 3 - D 22 OR2 0 4 1 0 |decode4_7:G6|:479
- 8 - D 22 OR2 0 4 1 0 |decode4_7:G6|:512
- 5 - D 22 OR2 0 4 1 0 |decode4_7:G6|:545
- 6 - D 22 OR2 0 4 1 0 |decode4_7:G6|:576
- 1 - B 08 DFFE 2 1 0 9 |mode_adjust:G1|c_state1 (|mode_adjust:G1|:19)
- 2 - B 08 DFFE 2 2 0 9 |mode_adjust:G1|c_state0 (|mode_adjust:G1|:20)
- 7 - B 08 AND2 0 2 0 3 |mode_adjust:G1|:537
- 5 - B 08 OR2 ! 0 2 0 2 |mode_adjust:G1|:545
- 5 - B 01 OR2 2 2 0 1 |mode_adjust:G1|:580
- 7 - B 01 OR2 2 2 0 1 |mode_adjust:G1|:592
- 6 - B 01 OR2 2 2 0 1 |mode_adjust:G1|:604
- 2 - B 10 OR2 s 0 2 0 2 |mode_adjust:G1|~616~1
- 2 - B 01 OR2 1 1 0 8 |mode_adjust:G1|:725
- 4 - B 01 OR2 1 1 0 8 |mode_adjust:G1|:731
- 3 - B 01 OR2 1 1 0 8 |mode_adjust:G1|:737
- 1 - B 10 OR2 2 1 1 0 |mode_adjust:G1|:743
- 4 - B 10 OR2 2 1 1 0 |mode_adjust:G1|:749
- 4 - B 08 OR2 2 1 1 0 |mode_adjust:G1|:755
- 8 - B 08 OR2 2 1 1 0 |mode_adjust:G1|:761
- 3 - B 03 OR2 2 1 1 0 |mode_adjust:G1|:767
- 2 - B 03 OR2 2 1 1 0 |mode_adjust:G1|:773
- 3 - B 08 OR2 1 2 0 1 |mode_adjust:G1|:779
- 6 - B 08 OR2 1 2 0 1 |mode_adjust:G1|:785
- 2 - B 02 OR2 ! 0 4 0 9 :64
- 6 - C 16 OR2 0 4 0 9 :66
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: g:\top1\clock.rpt
clock
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 2/ 72( 2%) 0/ 72( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
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