dll_4_map.vhd

来自「倍频详解」· VHDL 代码 · 共 173 行

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: J.30
--  \   \         Application: netgen
--  /   /         Filename: dll_4_map.vhd
-- /___/   /\     Timestamp: Thu Dec 06 16:26:48 2007
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -intstyle ise -s 6 -pcf dll_4.pcf -rpw 100 -tpw 0 -ar Structure -tm dll_4 -w -dir netgen/map -ofmt vhdl -sim dll_4_map.ncd dll_4_map.vhd 
-- Device	: 2s15tq144-6 (PRODUCTION 1.27 2006-10-19)
-- Input file	: dll_4_map.ncd
-- Output file	: D:\program\ISE\ISE+work\13\dll_4\netgen\map\dll_4_map.vhd
-- # of Entities	: 1
-- Design Name	: dll_4
-- Xilinx	: D:\Program Files\Xilinx91i
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Simulation Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity dll_4 is
  port (
    clk : in STD_LOGIC := 'X'; 
    clkout : out STD_LOGIC 
  );
end dll_4;

architecture Structure of dll_4 is
  signal clk_1 : STD_LOGIC; 
  signal clkout_OBUF_0 : STD_LOGIC; 
  signal clk2_fb : STD_LOGIC; 
  signal clk1_fb : STD_LOGIC; 
  signal CLK2X : STD_LOGIC; 
  signal LOCKED2X : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal clkout_OUTMUX_1 : STD_LOGIC; 
  signal U5_LOCKED : STD_LOGIC; 
  signal U5_CLKDV : STD_LOGIC; 
  signal U5_CLK270 : STD_LOGIC; 
  signal U5_CLK180 : STD_LOGIC; 
  signal U5_CLK90 : STD_LOGIC; 
  signal U5_CLK0 : STD_LOGIC; 
  signal U5_RST_INTERNALNOT : STD_LOGIC; 
  signal u1_CLKDV : STD_LOGIC; 
  signal u1_CLK270 : STD_LOGIC; 
  signal u1_CLK180 : STD_LOGIC; 
  signal u1_CLK90 : STD_LOGIC; 
  signal u1_CLK0 : STD_LOGIC; 
  signal u1_LOGIC_ZERO_2 : STD_LOGIC; 
  signal LOCKED2X_delay_LOGIC_ONE_3 : STD_LOGIC; 
  signal LOCKED2X_delay : STD_LOGIC; 
begin
  clkout_OBUF : X_OBUF
    port map (
      I => clkout_OUTMUX_1,
      O => clkout
    );
  clkout_OUTMUX : X_BUF
    port map (
      I => clkout_OBUF_0,
      O => clkout_OUTMUX_1
    );
  U5_RSTMUX : X_INV
    port map (
      I => LOCKED2X_delay,
      O => U5_RST_INTERNALNOT
    );
  U5 : X_CLKDLL
    generic map(
      CLKDV_DIVIDE => 2.0000,
      DUTY_CYCLE_CORRECTION => TRUE,
      MAXPERCLKIN => 40000 ps
    )
    port map (
      CLKIN => clk1_fb,
      CLKFB => clk2_fb,
      RST => U5_RST_INTERNALNOT,
      CLK0 => U5_CLK0,
      CLK90 => U5_CLK90,
      CLK180 => U5_CLK180,
      CLK270 => U5_CLK270,
      CLK2X => clkout_OBUF_0,
      CLKDV => U5_CLKDV,
      LOCKED => U5_LOCKED
    );
  u1_LOGIC_ZERO : X_ZERO
    port map (
      O => u1_LOGIC_ZERO_2
    );
  u1 : X_CLKDLL
    generic map(
      CLKDV_DIVIDE => 2.0000,
      DUTY_CYCLE_CORRECTION => TRUE,
      MAXPERCLKIN => 40000 ps
    )
    port map (
      CLKIN => clk_1,
      CLKFB => clk1_fb,
      RST => u1_LOGIC_ZERO_2,
      CLK0 => u1_CLK0,
      CLK90 => u1_CLK90,
      CLK180 => u1_CLK180,
      CLK270 => u1_CLK270,
      CLK2X => CLK2X,
      CLKDV => u1_CLKDV,
      LOCKED => LOCKED2X
    );
  LOCKED2X_delay_LOGIC_ONE : X_ONE
    port map (
      O => LOCKED2X_delay_LOGIC_ONE_3
    );
  u3_SRL16E : X_SRL16E
    generic map(
      INIT => X"0001"
    )
    port map (
      A0 => GLOBAL_LOGIC1,
      A1 => GLOBAL_LOGIC1,
      A2 => GLOBAL_LOGIC1,
      A3 => GLOBAL_LOGIC1,
      D => LOCKED2X,
      CE => LOCKED2X_delay_LOGIC_ONE_3,
      CLK => clk1_fb,
      Q => LOCKED2X_delay
    );
  GLOBAL_LOGIC1_VCC : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  clk_BUF : X_CKBUF
    port map (
      I => clk,
      O => clk_1
    );
  u2_BUF : X_CKBUF
    port map (
      I => CLK2X,
      O => clk1_fb
    );
  u6_BUF : X_CKBUF
    port map (
      I => clkout_OBUF_0,
      O => clk2_fb
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;