dffpipe_93c.tdf

verilog代码读写SDRAM 不带仿真

--dffpipe CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DELAY=0 WIDTH=32 d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
--VERSION_BEGIN 7.2SP2 cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratixii 2007:10:19:15:30:42:SJ cbx_util_mgl 2007:11:07:17:40:20:SJ  VERSION_END


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--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
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--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
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--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
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--  applicable agreement for further details.



--synthesis_resources = 
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";

SUBDESIGN dffpipe_93c
( 
	d[31..0]	:	input;
	q[31..0]	:	output;
) 

BEGIN 
	q[] = d[];
END;
--VALID FILE