状态机设计:8.1.1 数据类型定义语句TYPE语句的用法如下:TYPE 数据类型名IS 数据类型定义OF 基本数据类型;或TYPE 数据类型名IS 数据类型定义;TYPE st1 IS ARRAY ( 0 TO 15 ) OF STD_LOGIC ;TYPE week IS (sun,mon,tue,wed,thu,fri,sat) ; 8.1.1 数据类型定义语句TYPE m_state IS ( st0,st1,st2,st3,st4,st5 ) ;SIGNAL present_state,next_state : m_state ;TYPE BOOLEAN IS (FALSE,TRUE) ;TYPE my_logic IS ( '1' ,'Z' ,'U' ,'0' ) ;SIGNAL s1 : my_logic ;s1 <= 'Z' ;SUBTYPE 子类型名IS 基本数据类型RANGE 约束范围;SUBTYPE digits IS INTEGER RANGE 0 to 9 ;
标签: 状态
上传时间: 2013-11-05
上传用户:nem567397
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity counter is Port ( clk : in STD_LOGIC; resetn : in STD_LOGIC; dout : out STD_LOGIC_vector(7 downto 0); lcd_en : out STD_LOGIC; lcd_rs : out STD_LOGIC; lcd_rw : out STD_LOGIC); end counter;
上传时间: 2013-10-30
上传用户:wqxstar
VHDL编写的4选一数据选择器 entity mux41a is port(a,b:in STD_LOGIC; s1,s2,s3,s4:in STD_LOGIC; y: out STD_LOGIC); end entity mux41a; architecture one of mux41a is signal ab:STD_LOGIC_vector(1 downto 0);
上传时间: 2020-05-15
上传用户:cdga