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CPLD VHDL CODE非常好的参考资料

源代码在线查看: seg70.tan.summary

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关键词: CPLD CODE VHDL 参考资料
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相关代码

					--------------------------------------------------------------------------------------
					Timing Analyzer Summary
					--------------------------------------------------------------------------------------
					
					Type           : Worst-case tco
					Slack          : N/A
					Required Time  : None
					Actual Time    : 17.000 ns
					From           : lpm_counter:cnt_scan_rtl_0|dffs[15]
					To             : dataout[6]
					From Clock     : clk
					To Clock       : 
					Failed Paths   : 0
					
					Type           : Clock Setup: 'clk'
					Slack          : N/A
					Required Time  : None
					Actual Time    : 76.92 MHz ( period = 13.000 ns )
					From           : lpm_counter:cnt_scan_rtl_0|dffs[0]
					To             : lpm_counter:cnt_scan_rtl_0|dffs[0]
					From Clock     : clk
					To Clock       : clk
					Failed Paths   : 0
					
					Type           : Total number of failed paths
					Slack          : 
					Required Time  : 
					Actual Time    : 
					From           : 
					To             : 
					From Clock     : 
					To Clock       : 
					Failed Paths   : 0
					
					--------------------------------------------------------------------------------------
					
									

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